spread spectrum clock generato r sm560 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 document #: 38-07020 rev. *e revised june 25, 2004 features ? 25- to 108-mhz opera ting frequency range ? wide (9) range of spread selections ? accepts clock and crystal inputs ? low power dissipation ? 3.3v = 85 mw (50 mhz) ? frequency spread disable function ? center spread modulation ? low cycle-to cycle jitter ? eight-pin soic package applications ? vga controllers ? lcd panels and monitors ? printers and multi-function devices (mfp) benefits ? peak electromagnetic interference (emi) reduction by 8 to 16 db ? fast time to market ? cost reduction block diagram pin configuration pd vco 1 8 xin/ clk xout reference divider 4 pf 8 pf 250 k feedback divider modulation control divider and mux 5 2 3 7 vdd sscc sscl k vss 4 6 lf input decoder logic s1 s0 cp 1 2 3 4 8 7 6 5 xi n/clk vdd ssclk vss xout s0 s1 ssc c sm560
sm560 document #: 38-07020 rev. *e page 2 of 8 functional description the cypress sm560 is a spread spectrum clock generator (sscg) ic used for the purpose of reducing electro magnetic interference (emi) found in today?s high-speed digital electronic systems. the sm560 uses a cypress-proprietary phase-locked loop (pll) and spread spectrum clock (ssc) technology to synthesize and frequency modulate the input frequency of the reference clock. by frequency modulating the clock, the measured emi at the fundament al and harmonic frequencies of clock (ssclk1) is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regulat ory requirements and time to market without degrading the system performance. the sm560 is a very simple and versatile device to use. the frequency and spread% range is selected by programming s0 and s1digital inputs. these inputs use three (3) logic states including high (h), low (l) and mi ddle (m) logic levels to select one of the nine available frequency modulation and spread% ranges. refer to table 1 for programming details. the sm560 is optimized for svga (40 mhz) and xvga (65 mhz) controller clocks and also suitable for the applications with the frequency range of 25 to 108 mhz. a wide range of digitally selectable spread percentages is made possible by using three-level (high, low and middle) logic at the s0 and s1 digital control inputs. the output spread (frequency modulation) is symmetrically centered on the input frequency. spread spectrum clock control (sscc) function enables or disables the frequency spread and is provided for easy comparison of system performance during emi testing. the sm560 is available in an eight-pin soic package with a 0 to 70 c operating temperature range. pin definitions pin name type description 1 xin/clk i clock or crystal connection input . refer to table 1 for input frequency range selection. 2 vdd p positive power supply . 3 gnd p power supply ground . 4 ssclk o modulated clock output . 5 sscc i spread spectrum clock contro l (enable/disable) function . sscg function is enabled when input is high and disabled when input is low. this pin is pulled high internally. 6 s1 i tri-level logic input control pin used to select frequency and bandwidth . frequency/bandwidth selection and tri-level logic programming. see figure 1 . 7 s0 i tri-level logic input control pin used to select frequency and bandwidth . frequency/bandwidth selection and tri-level logic programming. see figure 1 . 8 xout o oscillator output pin connected to crystal . leave this pin unconnected if an external clock drives xin/clk. table 1. frequency and spread% selection (center spread) 25 ? 54 mhz (low range) input frequency (m hz) s1=m s0=m (% ) s1=m s0=0 (%) s1=1 s0=0 (% ) s1=0 s0=0 (% ) s1=0 s0=m (% ) 25 ? 35 3.8 3.2 2.8 2.3 1.9 35 ? 40 3.5 3.0 2.5 2.1 1.7 40 ? 45 3.2 2.8 2.4 1.9 1.6 45 ? 50 3.0 2.6 2.2 1.8 1.5 50 ? 54 2.8 2.4 2.0 1.7 1.4 50 ? 108 mhz (high range) input frequency (m hz) s1=1 s0=m (% ) s1=0 s0=1 (%) s1=1 s0=1 (% ) s1=m s0=1 (% ) 50 ? 60 2.5 1.9 1.2 1.0 60 ? 70 2.4 1.8 1.1 0.9 70 ? 80 2.3 1.6 1.1 0.9 80 ? 100 2.0 1.4 1.0 0.8 100 ? 108 1.8 1.3 0.8 0.6 select the frequency and center spread % desired and then set s1, s0 as indicated. select the frequency and center spread % desired and then set s1, s0 as indicated.
sm560 document #: 38-07020 rev. *e page 3 of 8 tri-level logic with binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using two control lines. tri-level logic in the sm560 is implemented by defining a third logic state in addition to the standard logic ?1? and ?0.? pins 6 and 7 of the sm560 recognize a logic state by the voltage applied to the respective pin. these states are defined as ?0? (low), ?m? (middle), and ?1? (one). each of these states has a defined voltage range that is interpreted by the sm560 as a ?0,? ?m,? or ?1? logic state. refer to table 2 for voltage ranges for each logic state. by using two equal value resistors (typically 20k) the ?m? state can be easily programmed. pins 6 or 7 can be tied directly to ground or vdd for logic ?0? or ?1? respectively . vdd = 3.3 vdc vdd = 3.3 vdc vdd = 3.3 vdc sm560 5 6 77 6 5 sm560 1.65 vdc 0 vdc sm560 7 6 5 ex. 1 ex. 2 ex. 3 20k 20k figure 1.
sm560 document #: 38-07020 rev. *e page 4 of 8 absolute maximum ratings [ 1 ] supply voltage (v dd ): .................................... ?0.5v to +6.0v dc input voltage:..................................?0.5v to vdd + 0.5v junction temperature ............. .............. ...... ?40c to +140c operating temperature:...................................... 0c to 70c storage temperature .................................. ?65c to +150c static discharge voltage (esd).......................... 2,000v-min. sscg theory of operation the sm560 is a pll-type clock generator using a proprietary cypress design. by precisely co ntrolling the bandwidth of the output clock, the sm560 becom es a low emi clock generator. the theory and detailed oper ation of the sm560 will be discussed in the following sections. emi all digital clocks generate unwant ed energy in th eir harmonics. conventional digi tal clocks are square waves with a duty cycle that is very close to 50%. beca use of this 50/50-duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e.; third, fifth, seventh, etc. it is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing the bandwidth of the funda - mental clock frequency. conventional digital clocks have a very high q factor, which means t hat all of the energy at that frequency is concentrated in a very narrow bandwidth, conse - quently, higher energy peaks. regulatory agencies test electronic equipment by the am ount of peak energy radiated from the equipment. by reduc ing the peak energy at the funda - mental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for emi. conventional methods of reducing emi have been to use shielding, filtering, multi-layer pcbs, etc. the sm560 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the q. sscg sscg uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle to cycle. the sm560 takes a narrow band digital reference clock in the range of 25?108 mhz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. to understand what happens to a clock when sscg is applied, consider a 65-mhz clock with a 50% duty cycle. from a 65-mhz clock we know the following: note: 1. single power supply: the voltage on any input or i/o pin cann ot exceed the power pin during power up. table 2. dc electrical characteristics: v dd = 3.3v, temp. = 25c and c l (pin 4) = 15 pf, unless otherwise noted parameter description conditions min. typ. max. unit v dd power supply range 10% 2.97 3.3 3.63 v v inh input high voltage s0 and s1 only 0.85v dd v dd v dd v v inm input middle voltage s0 and s1 only 0.40v dd 0.50v dd 0.60v dd v v inl input low voltage s0 and s1 only 0.0 0.0 0.15v dd v v oh1 output high voltage i oh = 6 ma 2.4 v v oh2 output high voltage i oh = 20 ma 2.0 v v ol1 output low voltage i oh = 6 ma 0.4 v v ol2 output low voltage i oh = 20 ma 1.2 v cin1 input capacitance xin/clk (pin 1) 3 4 5 pf cin2 input capacitance xout (pin 8) 6 8 10 pf cin2 input capacitance s0, s1, sscc (pins 7,6,5) 3 4 5 pf i dd1 power supply current f in = 40 mhz 30 40 ma i dd2 power supply current f in = 65 mhz 35 45 ma table 3. electrical timing characteristics: v dd = 3.3v, t = 25c and c l = 15 pf, unless otherwise noted parameter description conditions min. typ. max. unit iclkfr input clock frequency range v dd = 3.30v 25 108 mhz trise clock rise time (pin 4) ssclk1 @ 0.4 ? 2.4v 1.2 1.4 1.6 ns tfall clock fall time (pin 4) ssclk1 @ 0.4 ? 2.4v 1.2 1.4 1.6 ns dtyin input clock duty cycle xin/clk (pin 1) 20 50 80 % dtyout output clock duty cycle ssclk1 (pin 4) 45 50 55 % jcc cycle-to-cycle jitter fin = 25 ? 108 mhz - 125 175 ps
sm560 document #: 38-07020 rev. *e page 5 of 8 if this clock is applied to the xin/clk pin of the sm560, the output clock at pin 4 (ssclk) will be sweeping back and forth between two frequencies. these two frequencies, f1 and f2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at pin 1. as the clock is making the transition from f1 to f2, the amount of time and sweep waveform play a very important role in the amount of emi reduction realized from an sscg clock. the modulation domain analyzer is used to visualize the sweep waveform and sweep period. the left side of figure 2 shows the modulation profile of a 65-mhz sscg clock. notice that the actual sweep waveform is not a simple sine or sawtooth waveform. the right side of figure 2 is a scan of the same sscg clock using a spectrum analyzer. in this scan you can see a 6.48-db reduction in the peak rf energy when using the sscg clock. modulation rate spectrum spread clock gene rators utilize frequency modulation (fm) to distribute ener gy over a specific band of frequencies. the maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. the time required to transition from fmin to fmax and back to fmin is the period of the modulation rate, tmr. modulation rates of sscg clocks are gene rally referred to in terms of frequency or fmod = 1/tmod. the input clock frequency, fin, and the internal divider count, cdiv, determine the modulation rate. in some sscg clock generators, the selected range determines the internal divider count. in other sscg clocks, the internal divider count is fixed over the operating range of the part. the sm560 and sm561 have a fixed divider count, as listed below. tc = 15.4 ns 50 % 50 % c lock frequency = fc = 65mhz c lock period = tc =1/65 mhz = 15.4 ns device cdiv sm560 1166 (all ranges) sm561 2332 (all ranges) example: device = sm560 fin = 65 mhz range = s1 = 1, s0 = m then; modulation rate = fmod = 65 mhz/1166 = 55.8 khz. - 6.58 db modulation profile spectrum analyzer bw = 2.46% figure 2. sscg clock, sm560, fin = 65 mhz
sm560 document #: 38-07020 rev. *e page 6 of 8 sm560 application schematic the schematic in figure 3 above demonstrates how the sm560 is configured in a typical application. this application is using a 40-mhz reference derived from a third overtone crystal connected to pins 1 and 8. since y1 is a third overtone crystal a notch filter is creat ed with l1 and c3 to dampen the gain of the oscillator at the fundamental frequency of this crystal which is 13.33 mhz. figure 3 also demonstrates how to properly use the tri-level logic employed in the sm560. notice that resistors r2 and r4 create a voltage divider that places v dd /2 on pin 7 to satisfy the voltage requirem ent for an ?m? state. with this configuration, the sm560 will produce an sscg clock that is at a center fre quency of 40 mhz. referring to table 2 , range ?0, m? at 40 mhz will generate a modulation profile that has a 1.7% peak to peak spread. note: 2. the value of l1 is calculated such that l1 and c3 are tuned to a frequency that is 130% higher than the fundamental frequency of the crystal. zc1 = 1/2 fc zc1 = 1/6.28 (17.33 mhz) (27 pf) zc1 = 340 ? zl1 = 2 fl l = zl1/2 f l = 340/6.28(17.33 mhz) l = 3.12 h 3. the ordering part number differs from the marking on the actual device. vdd note 1. vdd vdd y1 40 mhz l1 3.3 uh. c3 27 pf c2 27 pf c5 22 uf. c4 .01 uf. c6 0.1 uf r4 20 k r2 20 k r5 22 application load sm560 xin/clk 1 vdd 2 gnd 3 ssclk 4 sscc 5 s1 6 s0 7 xout 8 figure 3. application schematic [2] ordering information [ 3 ] part number package type product flow imism560bz 8-pin soic commercial, 0 to 70 c IMISM560BZT 8-pin soic?tape and reel commercial, 0 to 70 c lead free devices cyism560bsxc 8-pin soic commercial, 0 to 70 c cyism560bsxct 8-pin soic?tape and reel commercial, 0 to 70 c marking: example: imi sm560bs date code, lot# sm560 b s package s = soic revision imi device number
sm560 document #: 38-07020 rev. *e page 7 of 8 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic - s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c 8-lead (150-m il) soic s8
sm560 document #: 38-07020 rev. *e page 8 of 8 document history page document title: sm560 spread spectrum clock generator document number: 38-07020 rev. ecn no. issue date orig. of change description of change ** 106948 06/07/01 ika convert from imi to cypress *a 113520 04/10/02 dmg package suffix changed (per cypress standard) *b 119445 10/16/02 rgl corrected the values in the absolute maximum ratings to match the device. *c 122675 12/14/02 rbi added power up requirements to operating conditions information. *d 231055 see ecn rgl added lead free devices *e 237630 see ecn rgl minor change: added letter c in the ordering for lead free
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